/*                                                                      
 Copyright 2018 hzheng@gzhu.edu.cn              
                                                                         
 Licensed under the Apache License, Version 2.0 (the "License");         
 you may not use this file except in compliance with the License.        
 You may obtain a copy of the License at                                 
                                                                         
     http://www.apache.org/licenses/LICENSE-2.0                          
                                                                         
  Unless required by applicable law or agreed to in writing, software    
 distributed under the License is distributed on an "AS IS" BASIS,       
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and     
 limitations under the License.                                          
 */                                                                      
/*+***********************************************************
Filename: zh_regfile_v01.v
Description: a simple register file implementation.
             with higher 16 registers assigned to I/O registers.
Modification:
  2018.07.28 createion by Zheng Hui
             modified from e203_exu_regfile.v (copyright see bottom)

************************************************************-*/

module zh_regfile_v01(
  input [4:0] i_rf_rs1idx,
  input [4:0] i_rf_rs2idx,
  output  [31:0] rf_rs1data,
  output  [31:0] rf_rs2data,

  output  [31:0] gpio1out,

  input [4:0] i_rf_rdidx,
  input i_rf_rdwen,
  input [31:0] i_rf_rd_data,

  input rst_n,
  input core_clk
);

wire [31:0] rf_r [31:0];
wire [31:0] rf_wen;

assign rf_r[0] = 32'b0;
assign rf_wen[0]=0;

wire rf_wr_clk;
assign rf_wr_clk=~core_clk;

  genvar i;
  generate //{
  
      for (i=1; i<32; i=i+1) begin:regfile//{
  
        assign rf_wen[i] = i_rf_rdwen & (i_rf_rdidx == i) ;
        sirv_gnrl_dfflr #(32) rf_dfflr (rf_wen[i], i_rf_rd_data, rf_r[i], rf_wr_clk, rst_n);
  
      end//}
  endgenerate//}

assign rf_rs1data = rf_r[i_rf_rs1idx];
assign rf_rs2data = rf_r[i_rf_rs2idx];

assign gpio1out = rf_r[16];

endmodule


//modified from e203_exu_regfile.v

 /*                                                                      
 Copyright 2017 Silicon Integrated Microelectronics, Inc.                
                                                                         
 Licensed under the Apache License, Version 2.0 (the "License");         
 you may not use this file except in compliance with the License.        
 You may obtain a copy of the License at                                 
                                                                         
     http://www.apache.org/licenses/LICENSE-2.0                          
                                                                         
  Unless required by applicable law or agreed to in writing, software    
 distributed under the License is distributed on an "AS IS" BASIS,       
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and     
 limitations under the License.                                          
 */                                                                      
                                                                         
                                                                         
                                                                         
//=====================================================================
//--        _______   ___
//--       (   ____/ /__/
//--        \ \     __
//--     ____\ \   / /
//--    /_______\ /_/   MICROELECTRONICS
//--
//=====================================================================
// Designer   : Bob Hu
//
// Description:
//  The Regfile module to implement the core's general purpose registers file
//
// ====================================================================